Taiwan Semiconductor Research Institute

Design File Export

Application Link

Guidelines and Instructions for Application to Design File Export Service：

	File Type	Reference File Extensions	Fee	Description
Service Lab(SL)	Only provide export of chip design files for type A accounts		NT$650
EDA Cloud	GDS	.gds	NT$650
	Circuit design diagram	.v .sp .netlist .edif	Export of the listed file types under a single EDA Cloud account, 10 files charged at NT$1,000	Text files describing circuit components and connections using Verilog, Spice, and other syntax. Verilog RTL/Gate-level netlist, Spice pre-sim netlist
	Standard component design specification file	.sdc		Text file describing standard component design specifications, timing specifications, timing exceptions, and related content.
	Testability verification file	.wgl .stil		Text files containing test requirements for circuit testability and generated test files.
	Test instrument input	.avc		Conversion of circuit simulation results to the required input format for test instruments.
	Layout verification text file			Text file providing layout verification check results in a textual format. For example, Calibre DRC/LVS verification reports.

Submit application

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Processing document/file inspection

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Approval of the order

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Download files

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Complete payment

Applicants (professors) must personally sign the "Application and Commitment Form for Design File Export" and upload the scanned copy of the signed document to the application system.
The invoice will list 'Data Retrieval Fee' as the item description, with the invoice heading designated as the school's name.
The online system has been providing external services since 2013. Design files uploaded to this system will be retained for 10 years from the application deadline. Designers are kindly advised to take note of this policy.