Applicants must be current students and meet the following criteria：

1. The professor has applied for process data from TSRI and received approval for its use.
2. Both the designer and co-designer have been authorized by the professor to use the process information.
3. The professor has missed the submission of fewer than three test reports, or fewer than six educational chip test reports.
4. The designer has not missed any submission of test reports.

For more detailed application procedures, please refer to：

1. Guidelines and Instructions for Applying for Advanced Ahip manufacturing
2. Guidelines and Instructions for Applying for Educational Chip Manufacturing

Currently, TSRI only accepts applications from teachers (lecturers and above) at colleges and universities. Applications are accepted on an annual basis. For detailed application procedures, please refer to：Guidelines and Instructions for Applying for the Use of Process Information.

log in to TSRI's website -> Chip Implementation -> Tape-out Application -> Tape-out New Application -> View Tape-out Qualifications -> and then click " 2. The records of your missing test report submissions. "
If you have any questions regarding the website information, please contact Ms. Yu at 03-5773693 extension 7219.

The oral presentation time for the designer is 20 minutes (including committee questions), typically allocated as follows：
  1. Overview of relevant research and development status and research motivation(2 mins)
  2. Introduction to the architecture and circuit design(5 mins)
  3. Simulation results(3 mins)
  4. Layout verification and packaging results(2 mins)
  5. Considerations for testing(2 mins)
  6. Committee inquiries(6 mins)

Presentation materials prepared by the designer can refer to：
Sample Presentation Slides for the Review Meeting

Please contact the relevant business coordinator by phone or email. For contact information, please refer to：
Chip manufacturing Service Coordinator or Point of Contact

Density errors cannot be disregarded. It's necessary to add dummy patterns in the remaining space within the chip to meet the density requirements. If density errors persist after adding dummy patterns, please contact respective process engineers for assistance. Do not attempt to rationalize it on your own.

For the T18 and TN90GUTM processes, a dummy OD/PO/metal pattern generation utility is available for designers to use.

The T18 and D35 processes provide complete layouts for STC I/O pads, along with related examples or explanatory documents. The D35 process provides TSMC I/O pads (pseudo-layout, required to be replaced with actual layouts through TSRI’s services).

In general, the top metal layer with a thicker metal has a lower sheet resistance (e.g., for a 1P6M process, the top metal would be metal 6).

"Nothing in layout" typically indicates an error in the component layout, which prevents Calibre from recognizing the devices and, as a result, it is unable to find objects for LVS verification.

The new version of Laker OA is now similar to Custom Compiler, functioning as an OA library and allowing the calling of Synopsys's iPDK. Similarly, Cadence's PDK is intended for use with Virtuoso and is also an OA library.
The older version of Laker had a distinct M-Cell functionality, operating as a lib++ library. Unlike an OA library, it cannot call upon PDK or iPDK.

Please refer to the website for specific information. The Design Rule Check (DRC) violation specifications for each process are outlined on the validation page.

In the netlist file, please add the library for capacitance and resistance (e.g., .lib 'xxx.l' pip/ .lib 'xxx.l' res...) to enable simulation. For specific library names, please refer to the process model files for each process.

For advanced designers or for advanced and high-frequency circuits, using electromagnetic simulation software to analyze parasitic effects is more accurate and appropriate than RC extraction method. Therefore, using electromagnetic simulation can be considered as completing post-layout simulation.

For the WIN 0.15um PHEMT process, the foundry only provides Diva DRC verification files. When performing layout verification, you need to copy the verification file (Dive Code) provided by WIN to the Rules Library. In addition, Diva DRC verification requires setting up related Switch Names for Rule Check. The result of the check should show "Total errors found: 0" individually. For detailed Diva DRC verification steps, please refer to the "WIN 0.15um PHEMT Layout Verification User Manual." To download the manual, please go to TSRI's homepage (login required) -> Chip Implementation -> Process/Silicon Intellectual Property(SIP) -> Technical Data Download -> Technical Information (select process name as P15) -> Application Documents. Document number: CIC-CIS-2008-MA33_P_v3.0

This is caused by the presence of dummy metal in the chip, but it should not affect the functionality of the circuit. If designers are concerned that the dummy metal may cause the problem of identifying the pin and orientations during wire bonding, they should appropriately add a top metal identification layer to the layout ensuring that the packaging facility can correctly locate the actual pins.

Users who apply for the TSMC 0.35um, or UMC 0.18um CMOS processes are eligible to use the process information for the applied process.This includes the CMOS Design Kit and CMOS MEMS Design Kit (classified under technical files) as well as the CMOS MEMS User Guide (classified under technical documentation).

Yes. Please select both "Use post-processing provide by TSRI" and "Handle post-processing independently" on the same application form.

Before submitting your design in the current process, please download the latest process version and make sure you are using the correct CMOS MEMS design kit's accompanying tf file (there are versions for both Laker and Cadence).

The DRC rules provided with the TSMC CMOS MEMS Design Kit already integrate the relevant CMOS process rules. Therefore, users do not need to perform additional CMOS process DRC rules. Please ensure that you are using the latest version of the DRC file before submitting your design. Since the DRC rules in the UMC 0.18um CMOS MEMS Design Kit are specific to the MEMS structure, users are required to perform separate verification of the DRC rules for the UMC CMOS process.

In CMOS processes, creating the PAD layer in the layout actually involves removing the passivation protection layer in that area. If the top metal layer exists in that area, it will be exposed to the air and can be used for subsequent wire bonding connections. If you are performing your own post-processing, you need to consider whether the etchant used in the post-process will etch the metal. If it does, you should not create the PAD layer. However, if you are using TSRI's post-processing services, you must strictly adhere to TSMC's design rules.

Due to the increasingly strict requirements for Design Rules Check (DRC) by the foundry, VIA layer-related DRC violations are prohibited in the layout files starting from the 112D MPW schedule in the T18 process. Therefore, such violations are not acceptable in the T18 process. However, as of now, the foundry has not explicitly stated that VIA layer-related DRC violations are prohibited in the D35 process. The use of VIA and Contact layers in a ring or checkerboard pattern for designing the etching area is still allowed, but the width and spacing of VIAs and Contacts must comply with the DRC rules. Oversized VIA or Contact widths or densities can lead to structural collapse in the chip, posing a significant risk of contamination during the manufacturing process.

First, please refer to the table of DRC rules that can be violated, as listed on the Step 5 web page under TSRI's Chip Implementation->tape-out guide. If the violated DRC rule is not listed in the table, please inform the MEMS process engineer before uploading the design file to determine if the DRC error affects the overall process stability. Please explain the reason for ignoring the DRC error in the design content report.

The DRC rules for the MEMS process primarily focus on the release of MEMS structures and the prevention of damage to the CMOS circuit. If there is a need to violate these rules due to specific requirements, please consult with the process engineer in advance to assess the associated risks and feasibility.

The top metal layer in CMOS processes is not allowed to be used as a hard mask because prolonged exposure to the etchant can lead to excessive polymer buildup, which may affect the etching process of other designers. Lower metal layers, on the other hand, can be used as a hard mask, but the retained thickness cannot be controlled. Designers with specific requirements for metal hard masks are strongly encouraged to discuss their needs with the MEMS engineer.

Currently, TSRI does not provide licenses for MEMS simulation software. Users can apply for software such as CoventorWare and Ansys through the National Center for High-performance Computing's iService system. Please refer to the following link: https://iservice.nchc.org.tw/nchc_service/index.php . Before using the service, you need to apply for an account. For account application or software usage-related questions, please contact the service personnel of the NCHC iService system.

Users can select the folder "MOMEMS35_Conventorware" from the EDA cloud within the D35 process. Inside, you will find MEMS process description files for use with CoventorWare simulation software, with the file extension ".proc".

Yes, you can. However, please ensure that DRC verification is conducted for the test devices before tape-out submission.

TSRI's post-processing steps employ dry etching with CHF3 gas to etch silicon nitride and oxide structures (with the application of an electric field, it is an anisotropic etching). Therefore, only vertical etching of the oxide layer is possible, followed by isotropic etching of the silicon substrate using SF6.

To obtain the process material parameter data, please contact the 0.18um/0.35um CMOS MEMS engineer and request a confidentiality agreement (two copies). After obtaining the signed agreement from your professor, please send it back to the engineer at TSRI. Once confirmed, the electronic files of the process material parameters will be sent to your professor. Additionally, UMC 0.18um CMOS MEMS process currently does not provide related process material parameters.

Starting from the D35-103B version, TSRI merged the MEMS35 process with the BioMEMS35 process into the 0.35um Multi-Option MEMS process. For users of the original MEMS35 process, the previous definition of oxide and silicon etching areas using the RLS layer has been expanded to allow separate definition of oxide and silicon etching areas using both the RLS layer and the RLSSI layer, providing more flexibility in the process. For users of the original BioMEMS35 process, the Multi-Option MEMS process can be regarded as including BioMEMS, at the same time, layout drawing is not affected. For detailed layout design instructions, please refer to document number "TSRI-CIS-2019-AP002_P_v4.0" with the title "0.35um CMOS Multi-Option MEMS Process.pdf."

Yes, when drawing the layout, please use the RLS and RLSSI layers to separately define the areas where oxide and silicon need to be etched. If you only need to etch the oxide layer without etching the silicon layer, do not define the RLSSI layer in the layout.

No, please do not name the cell for bonding pads "pad" or "PAD" as these names are reserved for internal use by TSMC. If you use "PAD" as the cell name, it will be automatically replaced by TSMC with an 80*80um bonding pad. Please check carefully before submission if you have used cells with the same names as those in the TSMC I/O Library.

The thickness of the chip is approximately 533um when completed in the TSMC process. There may be slight variations in thickness between every MPW schedule. TSRI can provide the average value for reference, but for more accurate chip thickness data, it is recommended to measure it using a thickness gauge after receiving the chip.

Currently, it is not possible to add an extra metal layer on top of the poly layer in the 0.35um CMOS MEMS process. If you need to add a metal layer on top of the poly layer, you will have to perform post-processing to etch away the oxide layer and expose the poly layer, and then deposit the additional metal layer.

No, the process does not effectively deposit metal on the sidewalls.

The thickness of the gold layer is approximately 3000A.